1. Field of the Invention
The present disclosure relates to a clock and data recovery circuit and a method of recovering clock and data from a received signal and, more particularly, to circuits and methods of clock and data recovery which perform random edge sampling every predetermined number of data periods.
A claim of priority is made under 35 U.S.C. §119 from Korean Patent Application 10-2006-0122267, filed on Dec. 5, 2006, the contents of which are hereby incorporated by reference in their entirety.
2. Description of the Related Art
Two types of communication methods are predominantly used in the communication industry. These two communication methods are serial communications and parallel communications. Serial communication methods use serial interface devices to conduct serial communication. Similarly, parallel communication methods use parallel interface devices to conduct parallel communication. In general, a serial interface device is more popular than a parallel interface device in a high speed communications. This is because a maximum transmission distance and speed are limited in the parallel interface device due factors such as, for example, crosstalk, noise coupling, etc., between respective bits of transmitted and received data.
Serial interface devices may be used to transmit and receive data configured for parallel communication. In particular, the serial interface device converts parallel type data into a serial type and transmits it. Furthermore, the serial interface device may also be configured to receive serial data that includes parallel data information and then converts it into parallel information.
Unlike a parallel interface device that transmits clock and data simultaneously and individually, the serial interface device transmits only a data signal. This data signal transmitted by the serial interface device includes clock information. In particular, a transmitting serial interface device transmits a data signal by adding clock information to the data information and then transmitting the clock and data information in one data signal. Similarly, on the receiving end, a receiving serial interface extracts clock and data information from the received data. To this end, a clock and data recovery (CDR) circuit is generally used to perform a function of extracting clock and data from a data signal containing clock information.
FIG. 1 is a block diagram of a conventional clock and data recovery circuit. As shown in FIG. 1, a conventional CDR circuit includes a phase detector 10, a filter 20, and a voltage controlled oscillator (VCO) 30.
The phase detector 10 compares a phase of a data signal Data with a phase of a clock signal CLK generated in the VCO 30, and generates an error signal, that is, an Up signal or a Down signal.
The filter 20 may include a charge pump circuit, and receives the error signal. When the error signal is an Up signal, the filter 20 increases a level of a voltage control signal Vctrl, and when the error signal is a Down signal, a level of the voltage control signal Vctrl decreases.
The VCO 30 controls a phase of clock signal CLK according to a voltage level of voltage control signal Vctrl. When the level of the voltage control signal Vctrl increases, a phase or frequency of the clock signal CLK increases, and when the level of the voltage control signal Vctrl decreases, a phase or frequency of the clock signal CLK decreases.
The phase detector 10 reduces a phase difference between the data signal Data and the clock signal CLK by generating an error signal based on the phase difference between the data signal Data and the clock signal CLK. In particular, the phase detector 10 attempts to synchronize the data signal Data and the clock signal CLK.
FIG. 2 illustrates timing operations for a conventional data recovery procedure. As shown in FIG. 2, four bits of data are transmitted in one cycle of a reference clock signal CK. In order to recover data information from a received signal, two kinds of clocks are normally used. These clocks include a data clock Data0, Data1, Data2, Data3 positioned in a center of data and an edge clock Edge0, Edge1, Edge2, Edge3 for extracting edge information of data.
In general, when the data clock Data0, Data1, Data2, Data3, and the edge clock Edge0, Edge1, Edge2, Edge3 are generated successively, the phase difference between a successive data clock and edge clock is about half a data period. For example, a data clock Data0 and an edge clock Edge1 have a phase difference corresponding to a half of data period. Thus, when a phase of an edge clock is controlled so that the edge clock Edge0, Edge1, Edge2, Edge3 is precisely locked to a data edge, the data clock Data0, Data1, Data2, Data3 is always positioned dead center between data edges. That is, the data clock is positioned in the center portion of a data value. This may lead to a relatively large margin between the data clock and edge clock. Received data is then latched within a given interval by using the two kinds of clocks, and data latched by the data clock Data0, Data1, Data2, Data3 is output as effective data.
Beneficially, jitter generated in data may be reduced by extracting, in a real time, edge information every data period and by moving a phase of the clock signal according to the extraction result. However, the rate at which the phase of a clock may be changed is limited due delays in the feedback circuit shown in FIG. 1.
Therefore, phase information is extracted every data period, and the phase information for each data period is synthesized over several data periods. The phase change of the clock is decided based on this synthesized information. For example, as shown in FIG. 2, the phase change of clock is decided on the basis of phase information synthesized during four data periods.
The phase detector 10 shown in FIG. 1 can be realized as shown in FIGS. 3 to 5. The configuration and operation of a conventional phase detector will be now described under an assumption that the phase change of a clock will occur over four data periods.
Referring to FIG. 3, the phase detector 10 of the conventional CDR circuit includes four D-flip flops F0, F1, F2, and F3 for a data sampling, four D-flip flops F4, F5, F6, and F7 for an edge sampling, a decoder 12 and an adder 16.
Flip flops F0, F1, F2, and F3 latch input serial data with a given interval in response to each of data clock signals CLK_0, CLK_90, CLK_180, and CLK_270 having mutually different phases, thus generating sampling data Data0, Data1, Data2, and Data3.
The four D-flip flops F4, F5, F6 and F7 for the edge sampling operate in response to each of edge clock signals CLK_45, CLK_135, CLK_225, and CLK_315 having mutually different phases. Furthermore, the D-flip flops F4, F5, F6, and F7 latch edges of input serial data with a given interval in response to the edge clock signals CLK_45, CLK_135, CLK_225, and CLK_315, thus generating edge sampling signals Edge0, Edge1, Edge2, and Edge3.
In general, the decoder 12 receives sampling data Data0, Data1, Data2, Data3, and edge sampling signals Edge0, Edge1, Edge2, Edge3. Furthermore, the decoder 12 determines whether a transition of the sampling data Data0, Data1, Data2, Data3 is generated or not, and extracts edge information from the edge sampling signal Edge0, Edge1, Edge2, Edge3. This will be described in detail with respect to FIG. 4.
FIG. 4 is a circuit diagram of the decoder 12. The decoder 12 includes a plurality of XOR logic circuits XO12, XO14, XO16, XO18, XO20, XO22, XO24, and XO26, inverter circuits I12, I14, I16, I18, I20, I22, I24, and I26, and AND circuits A12, A14, A16, A18, A20, A22, A24, and A26.
The decoder 12 includes sub-decoder circuits 12a, 12b, 12c, and 12d corresponding to the number of the edge sampling signals Edge0, Edge1, Edge2, and Edge3. One sub-decoder circuit 12a will be provided as an example whose configuration and operation will be described as follows.
One sub-decoder circuit 12a selects two consecutive sampling data Data0 and Data1 and an edge sampling signal Edge0. Then, the sub-decider circuit 12a performs a logic operation on the selected sampling data and the edge sampling signal. In detail, when the selected sampling data Data0 and Data1 correspond to data clock signals CLK_0 and CLK_90, the edge sampling signal Edge0 corresponding to an edge clock signal CLK_45 that has a middle phase value of the data clock signals CLK_0 and CLK_90, is selected.
Furthermore, the two selected sampling data Data0 and Data1 are input to a first XOR circuit XO12. Circuit XO12 determines whether a transition was generated or not between the sampling data Data0 and Data1. For example, when a sampling data Data0 is ‘0’ and a sampling data Data1 has ‘1’ or vice versa, it is decided the transition was generated, but when the sampling Data0 and Data 1 have the same value, it is decided that the transition was not generated. In other words, when an output signal of first XOR circuit XO12 has a value of ‘1’, it indicates a generation of transition, and when the transition is not generated, a hold signal Hold0 is generated.
When a transition is generated between the sampling data Data0 and Data1, the sampling data Data1 and the edge sampling signal Edge0 are logically operated on by a second XOR circuit XO14. Furthermore, edge information is extracted by performing a logic operation on the output signals of the second XOR circuit XO14 and the first XOR circuit XO12. In other words, the edge information is extracted by AND-operating output signals of the second XOR circuit XO14 and the first XOR circuit XO12, or by AND-operating an inverted signal of output signal of the second XOR circuit XO14 and an output signal of the first XOR circuit XO12. In particular, edge information as to whether an edge was precisely detected, is detected, through an output signal Early0 of the first AND circuit A12 that AND-operates output signals of the second XOR circuit XO14 and the first XOR circuit XO12, and through an output signal Late0 of the second AND circuit A14 that AND-operates an inverted signal of output signal of the second XOR circuit XO14 and an output signal of the first XOR circuit XO12. Specifically, this edge information is edge information between the sampling data Data0 and Data1. Similarly edge information between the rest sampling data, Data1 and Data2, Data2 and Data3, Data3 and Data0, is also detected through the other three sub-decoder circuits 12b-12d. 
Transition information Hold0, Hold1, Hold2, Hold3 and edge information Early0, Early1, Early2, Early3, Late0, Late1, Late2, Late3 of the sampling data Data0, Data1, Data2, Data3, output from the decoder 12, are input to the adder 16 as shown in FIG. 3. The adder 16 determines a mean of the edge information, and decides a phase change direction of the data clock signal and the edge clock signal based on the determined mean of the edge information.
The configuration and operation of the adder 16 are will now be described referring to FIG. 5. The adder 16 includes a plurality of shifters S0, S1, S2, and S3, with a wiring structure as shown in FIG. 5.
As shown in FIG. 5, the shifters S0, S1, S2, and S3 each receive the transition information Hold0, Hold1, Hold2, Hold3, and edge information Early0, Early1, Early2, Early3, Late0, Late1, Late2, Late3, output from the decoder 12, and perform an addition thereof. When the edge information Early0, Early1, Early2, Early3, Late0, Late1, Late2, Late3 is input, the shifter S0, S1, S2, S3 shifts, by 1 bit, previously input information of ‘11110000’. For example, when edge information is input as Early0=‘1’ Late=‘0’, a 0th shifter S0 shifts the information of ‘11110000’ and outputs it as ‘11100000’. On the contrary, when edge information is input as Early0=‘0’ Late=‘1’, the 0th shifter S0 outputs it as ‘11111000’.
The output from the last shifter S3 is logically operated on, and then the result is output. In particular, when an output of an inverter circuit 142 is ‘1’, a phase of the clock becomes down, and when an output signal XO42 of an XOR circuit is ‘1’, the phase is fixed, and when an up signal is generated, the phase of the clock becomes up. Furthermore, an output signal of the adder 16 is input to a voltage controlled oscillator 30 of FIG. 1, to control a phase of the clock.
As described above, a conventional CDR circuit extracts phase information every data period, and synthesizes the results over several data periods, and decides a phase change direction of the clock. However, the conventional CDR circuit has several limitations. For example, at high data transmission rates, the conventional CDR circuit must process data at a high speed for sampling data information and edge information. However, the sampling speed of a CDR circuit is limited by the operating speed of the internal components of the CDR circuit such as, for example, shifters, and logic gates. Therefore, in order to perform sampling at high speeds, the number of components may be to be increased. As the number of CDR circuits increases, a number of problems may occur. For example, the total current consumption for the CDR circuits may increase.
The present disclosure is directed towards overcoming one or more shortcomings of the conventional CDR circuits.